系统芯片测试调度模型及其调度算法

A Test Schedule Model and Corresponding Algorithm for SoCs

系统芯片的设计是基于IP核的设计,整个芯片的测试包括各个IP核和粘合逻辑的测试.根据测试基准模型ITC02建立了系统芯片测试调度模型,该模型假定系统芯片的每个模块有若干个可供选择的测试资源,已知使用每个测试资源所完成该测试的时间和功耗.在最大功耗约束下,提出了一种通用的测试调度算法,并针对构造的基准电路,给出了该调度算法的实现结果.

SoC design is based on IP core methodology and the test for the whole IC contains the tests for all the embedded cores and the glue logics. Test schedule algorithm is modeled based on ITC02 test benchmarks. It is supposed that a SoC is composed of many cores, and each of them has some available test resources, and the power dissipation and the time of each test are known. Under the maximum power constrain, a universal test schedule algorithm is proposed. The realized results of the test schedule algorithm according to the constructed benchmarks are presented.