基于FPGA的USB控制器IP核设计

Design for IP Core of USB Controller Based on Nios Ⅱ

根据USB1.1通信协议,设计基于AlteraFPGA的USB控制器核,包括接口电路设计,USB控制器设计。其接口电路负责连接USB控制器和微控制器,实现微控制器总线与SIE控制总线和EP0总线上的信号转换;USB控制器实现SIE控制、端点、EP0及收发器总线上信号的转换。所有信号都是由采用带清除预置功能的DFF触发器实现的,信号与信号的转换都是由组合逻辑电路来实现的。

According to specifications of USBI.1 protocol, design IP core of the USB controller based on Altera FPGA, which include the design of interface circuit and USB controller. The main function of interface circuit connects MCU and USB controller, realizes signal conversion between MCU bus and SIE, EP0 bus. USB controller mainly achieves signal conversion between the SIE, endpoint, EP0 bus and transceiver bus. All signals are composed of DFF Trigger and conversion beyond them is implemented by combinational logic circuit.