一种高精度低功耗流水线ADC开关电容电路

A High Accuracy and Low Power Switch-Capacitor Circuit for Analog-to-Digital Converter

提出一种新的电容失配校正方案及功耗驱动的OTA设计思路,通过对虚地电容的修正,将电容失配因子在取样保持系统中去除,达到提高电容匹配程度,降低OTA增益误差的要求,使开关电容部分的瞬态功耗下降.本文采用TSMC 0.18μm工艺设计了一个8位,取样速率为200MHz的流水线结构模数转换器作为验证电路,仿真结果说明此优化结构符合高精度和低功耗要求,可应用到流水线等高速模数转换电路中作为信号前端处理模块使用.

A novel approach of sample and hold amplifier for pipelined analog-to-digital converter is proposed based on the analysis of the non-idealities of traditional SHA. The capacitor mismatch error can be suppressed by the new architecture of SHA leading to the optimization of power and accuracy. This paper also brings forward the notion of power-driven method to design OTA based on the capacitor mismatch method proposed in this paper. A 200 MHz, 8 bits pipelined ADC with low power dissipation under TSMC 0.18 μm is adopted to evaluate the new toopology of the SHA.