一种新型低噪声电流控制逻辑的分析与设计

Analysis and Design of A Novel Low Noise Current-Steering Logic

本文绘出了一种新型电流控制逻辑的电路结构和工作原理，并由此提出了该逻辑的优化设计方法。通过采用恒定工作电流和限制电路的输出逻辑摆幅，电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。理论分析和电路模拟结果都表明，和静态CMOS电路相比，电流控制逻辑的峰值开关电流下降了近两个数量级．该逻辑可应用在高性能的模／数混合集成电路中。

A novel low noise current-steering logic structure and its principle are presented in this paper. Using a constant biasing current and a reduced output logic swing, current-steering logic avoids the large digital switching noise of conventional static CMOS logic. This paper also presents an optimized design methodology for this new logic family. Theoretical analysis and simulation results show that in this new logic, the power supply current spikes are about two orders of magnitude smaller than those generated in static CMOS.It is suitable to be used in high Performance mixed-mode ICs.