高速可重构AES的设计与实现

Design and implementation of high speed reconfigurable AES

提出一种可重构AES硬件架构,对加/解密运算模块和密钥扩展模块进行了可重构设计,使其能够适配128bit、192bit、256bit三种密钥长度的AES算法,并针对列混合模块进行了结构优化。在FPGA上进行了验证与测试,并在0.18μmSMIC工艺下进行了逻辑综合及布局布线。结果表明其核心时钟频率为270MHz,吞吐量达到3.4Gb/s,能够满足高性能的密码处理要求。

This paper presents a reconfigurable architecture of AES （Advanced Encryption Standard） algorithm. It has made a reconfigurable design of the operation module and the key expansion module which can supply all the three kinds of AES key length, and presented a structure optimization for the mixcolumn module. Then the design was validated and tested on FPGA, and a chip implementation using 0.18μm CMOS technology was done. The observed data throughput rate was 3.4Gb/s with a 270MHz clock.