CMP体系结构上非包含高速缓存的设计及性能分析

Design and performance analysis of non-inclusive cache on CMP

半导体技术的发展使得在芯片上集成数十亿个晶体管成为可能。目前工业界和学术界倾向于采用片上多处理器体系结构(CMP),对于此类结构,芯片性能受片外访存影响较大,因此如何组织片上高速缓存层次结构是一个关键。针对此问题,提出采用非包含高速缓存组织片上最后一级高速缓存,以降低片外访存次数。并通过对Splash2部分测试程序的详细模拟,对CMP上高速缓存层次结构的不同组织方式做了比较。数据显示非包含高速缓存最多可使平均访存时间降低8.3%。同时,指出非包含高速缓存有助于节省片上资源的特性,并给出片上集成三级高速缓存后CMP上高速缓存层次结构的设计建议。

As semiconductor technology develops, it is possible to pack billions of transistors on a single die. How to utilize such a large resources budget efficiently has been on-going for years. There is clear evidence of the trend that more and more commercial offerings and research projects address chip multiprocessors （CMP） design. Many design options on how to organize cache hierarchy before hitting memory wall to raise the performance, of CMP architecture are presented and non-inclusive cache is one of those. After evaluating several different organizations of cache hierarchy on CMP with partial Splash2 benchmarks, the result shows that non-inclusive cache can get benefits of 8.3% improvement in average data access time from reducing off-chip access. As non-inclusive cache can also save on-chip resources, it is proposed to improve CMP＇s performance by organizing the last line of defense of cache hierarchy with non-inclusive cache before going off-chip.