基于CTGAL电路的进制可变计数器设计

Design of Scale Alterable Counter Based on CTGAL Circuit

通过对计数器和钟控传输门绝热逻辑(clocked transmission gate adiabatic logic,CTGAL)电路工作原理及结构的研究,提出了基于CTGAL电路的四/八/十六进制可变计数器设计方案,与传统CMOS电路实现的四/八/十六进制计数器相比,在相同工作频率下,平均节省能耗约87%。HSPICE模拟结果表明了所设计的电路具有正确的逻辑功能和显著的低功耗特性。

Through the study of the working principle and structure of counter and Clocked Transmission Gate Adiabatic Logic （CTGAL） circuits, a design scheme of 4/8/16 scale alterable counter was proposed, which can save up to about 87% energy compared to traditional CMOS 4/8/16 counter atthe same frequency. HSPICE simulation resuits verified the valid functionality and the significant low-power characteristic of the designed circuits.