摘要
以减少系统芯片SOC测试时间为目标,研究了层次型SOC的多层次TAM优化问题。根据嵌入式IP核的分类,将层次型SOC测试结构优化转变成了平铺型SOC测试结构优化,并建立了基于量子进化算法的数学模型。通过对群体的观测,决定IP核在测试访问机制上的分配以及当前群体中的最佳个体,实现了包含TAM-ed且wrapped的嵌入式核的层次型SOC测试结构优化。针对国际标准片上系统芯片验证表明,与GA、ILP和启发式算法相比,该算法能够获得更短的测试时间。
Multilevel Test Access Mechanism(TAM) optimization is studied for the hierarchieal SOC while aimiug at reduction of test application time of system-on-a-chip. According to the classification of embedded IP cores, the optimization of hierarchical SOC test architecture is transfurmed into the optimization of flow SOC test architecture and a mathematical model using quantum-inspired evolutionary algorithm is set up. By observing the state of swarm, the results observed represent the assignment of IP core on test access mechanism and the best chromosome in current swarm. The paper realizes the optimization of hierarchical SOC test architecture while the hierarchical SOC including TAM-ed and wrapped embedded cores. The experimental results for SOC benchmark show that the proposed algorithm holds a shorter testing time when compared to the GA, ILP and heuristic algorithm.
出处
《计算机工程与应用》
CSCD
北大核心
2008年第14期96-99,共4页
Computer Engineering and Applications
基金
国家自然科学基金(the National Natural Science Foundation of China under Grant No.60266001)
广西自然科学基金(the Natural Science Foundation of Guangxi of China under Grant No.桂科自0542051)
关键词
量子进化算法
测试结构
层次型SOC
quantum-inspired evolutionary algorithm
test architecture
hierarehical SOC