期刊文献+

基于FPGA的多路数字量采集模块设计 被引量:10

Design of multi-channel digital signal collecting module based on FPGA
下载PDF
导出
摘要 针对测控系统中监测信号较多的情况,提出了一种基于FPGA的多路数字信号采集模块设计。采集数字信号的高低状态和测量其中一路信号的频率,并采集脉冲信号的脉宽和时延,通过FPGA将数据编帧上传给上位机。结合FPGA、大容量FIFO的特点,设计了光电隔离电路、FIFO电路、FPGA配置电路等。实现了USB2.0与上位机通信,通过上位机应用软件和驱动程序实现模块与PC机实时通信和控制。该设计方案结构灵活、控制简单、可靠性较高。 Aiming at the condition that there are many the momitoring signals in the monitor system,this paper introduces a multi-channel digital signal collecting module which takes FPGA.This module collects low or high state of the digital signals and one of the signals' frequency,collects the pulse signals' delay and width.The FPGA makes data into frame structure then uploads to the computer.With the characteristic of FPGA and mass capability FIFO,we design the circuit of optoelectronic coupler, FIFO and configure of FPGA.We can control and communicate the module with PC real-time within USB2.0 interface. The design scheme is easily modified, controlled and high reliability.
出处 《国外电子元器件》 2008年第5期47-49,52,共4页 International Electronic Elements
基金 国家自然科学基金重点项目(50535030)资助
关键词 FPGA 数字信号 电平 帧结构 XC2S100E FPGA digital signal electrical level frame structure XC2S100E
  • 相关文献

参考文献3

二级参考文献22

  • 1孙华锦,高德远,樊晓桠,张盛兵.32位微处理器总线接口部件的设计[J].西北工业大学学报,2004,22(3):370-374. 被引量:2
  • 2杨成伟,霍玉晶,陈千颂,赵大龙,秦来贵,张宝顺.CPLD在自触发脉冲激光测距飞行时间测量中的应用[J].量子电子学报,2005,22(6):914-917. 被引量:3
  • 3胡广书.正弦信号抽样中若干基本问题的讨论[J].清华大学学报(自然科学版),1997,37(1):74-77. 被引量:16
  • 4Metra C et al. Novel technique for testing FPGA. Design, Automation and Test in Europe, Palais des Congres Paris, France,1998, pp,89-94.
  • 5Alderighi M, Gummati E, Piuri V, Sechi G. A FPGA based implementation of a fault tolerant neural architecture for photon identification. In Proc. the Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, USA, 1997, pp.166-172.
  • 6Renovell M, Figueras Jl Zorian Y. Test of RAM-based FPGA: Methodology and application to the interconnect. In Proc,15th VLSI Test Sy,p., Anaheim, USA, 1997, pp,230-237.
  • 7Stroud C, Wijesuriya S, Hamilton C, Abramovici M. Built-in self-test of FPGA interconnect. In Proc. the IEEE Int. Test Conf., Washington DC, USA, 1998, pp.404-411.
  • 8Sun X, Xu J, Trouborst P. Testing Xilinx XC4000 configurable logic blocks with carry logic modules. In Proc. the IEEE Int. Syrnp, Defect and Fault Tolerance in VLSI Systems, San Francisco, CA, USA, October 2001,pp.221-229.
  • 9Renovell M, Portal J M, Figueras J, Zorian Y. RAM-based FPGAs: A test approach for the configurable logic. In Proc. the Design, Automation and Test in Europe, Palals des Congres Paris, France, 1998, pp,82-88.
  • 10Huang W K, Meyer F J, Park N, Lombardi F. Testing memory modules in SRAM-based configurable FPGAs. In Proc. IEEE International Workshop on Memory Technology, Design and Test, San Jose, CA, USA, August 1997, pp.79-86.

共引文献64

同被引文献46

引证文献10

二级引证文献36

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部