一种多码率QC-LDPC码译码结构设计与实现

Design and implementation of multi-rate quasi-cyclic low-density parity-check code decoder

为了满足在一个系统中使用多码率LDPC(LowDensity Parity Check)码字的需求,设计了一个7 Kbit长度多码率LDPC码的译码器,分析了各种码率之间校验矩阵的相似性,提出了复合译码结构中变量节点运算单元、校验节点运算单元以及迭代存储器单元的复用方案.通过在变量节点运算单元以及校验节点运算单元输入端增加若干选通开关,就可以使这些运算单元适于多码率的处理.通过管脚的选择,此译码器支持非规则0.4码率、非规则0.6码率以及非规则0.8码率3种工作译码模式,并用Altera公司的FPGA进行了实现.综合结果表明,所提出的复合结构在不损伤单码率译码性能的前提下,仅用略多于0.8码率LDPC码单独译码的硬件资源实现了3种码率码字的译码.

To meet the requirement of using multi-rate low density parity check （LDPC） codes in the communication system, a 7 Kbit code length multi-rate LDPC codes decoder architecture was presented and implemented on a Altera field-programmable gate array device. The similarity between different check matrixes of different rate was analyzed and the variable node processing unit （VNU）, the check node processing unit （CNU） and the iteration storage location duplication in the decoder were explained. By adding several switches in the input ports of the VNUs and the CNUs, these processing units can work under different code rates. Using pin selection, three operating modes, namely, the irregular 0.4 code mode, the irregular 0.6 code mode and the irregular 0.8 code mode, are supported. The synthesis result indicates that the proposed multirate LDPC code decoder using just a little more resources than a single 0.8 rate LDPC code decoder without any performance loss.