摘要
本文分析了深亚微米后端设计流程,提出基于层次法实现芯片后端设计的方法,并且在0.18um CMOS工艺下实现6百万门的EOS芯片。在超大规模的芯片后端设计中,层次法设计方法优于展平法的设计方法。
Based on the analysis of the IC design flow, a hierarchical method in VLSI backend design is proposed. This method was implemented with EOS backend design in 0.18um CMOS process. It shows that hierarchical method is better than flatten method in very large scale IC backend design.
出处
《微计算机信息》
北大核心
2008年第14期5-7,共3页
Control & Automation
关键词
后端设计
IC设计
层次法
EOS
Backend design
EOS
Hierarchical method
IC design
