基于FPGA流水线RISC微处理器的设计

Design of RISC Microprocessor with Pipelining Based on FPGA

文章介绍了基于FPGA的流水线RISC微处理器的设计,包括关键模块设计和流水线设计。所设计的微处理器主要由ALU,译码单元,取指逻辑,寄存器堆,指令存储器,数据存储器等关键模块组成,其指令和数据长度都为32位,采用三种寻址方式。通过对关键模块的时序分析,设计合理的流水线。文章着重分析了因流水线产生的相关性问题,并采用旁路技术(Forwarding)和硬件"猜测法"加以解决。综合和功能仿真结果表明该RISC处理器达到了设计要求,其最高时钟频率达到74.59MHz。

This paper introduces the design of RISC microprocessor with pipelining based on FPGA, which is included the design of key modules and pipelining. This microprocessor mainly consists of ALU, decoder, fetch logic, register bank, program memory, data memory, and so on. Both instruction and data length is 32 bit, and three kinds of addressing are adopted. An appropriate pipelining is designed through the timing analyses of key module. It has analyzed the pipeline hazards, which is solved via Forwarding and hardware ＂guess＂. According to the synthesis and the function simulating, the microprocessor is satisfied, and its frequency reaches 74.59 MHz.