基于FPGA的视频传输流发送系统设计

Design and Implementation of a New Kind of High-Speed Asynchronous Serial Interface with FPGA

介绍了一种利用FPGA实现DVB—ASI视频传输流发送系统的组成原理和实现方法。不同于使用Cypress公司的CY7B923的方法,使用FPGA编程实现ASI接口转换与发送功能,具有更大的灵活性,且接口复合DVB-ASI接口规范,可实现270Mbps的Mpeg2传输流传输。文中介绍了ASI的特点与构成;并详细阐述了使用FPGA实现ASI高速接口的硬件实现方法,最后给出了相应的测试实验。通过高清编码器和解码器的测试实验表明设计的正确性与可靠性。

The design and the implementation of a new kind of high-speed asynchronous serial interface （ASI） using FPGA are presented Different from the method based on CY7B923 of CYPRESS, the method based on FPGA programming provides more flexibility and realizes the sending and receiving of Mpeg2 transport stream. It conforms to the DVB-ASI standard and realizes theMpeg2 transport stream delivery. The feature and the structure of ASI are first described. Then the hard ware architecture and the implementation of DVB-ASI are illustrated in detail. Finally the experimental results are presented. Through experimentation of high definition encoder and decoder, the correctness and reliability of the design are confirmed.