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采用改进电流调制功耗缩放的精度和速度可编程流水线模数转换器 被引量：1

A Novel Sampling Precision and Rate Programmable Pipeline ADC with Improved Current Modulated Power Scaling
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摘要 介绍了一个精度和速度可编程、但不需要改变运算放大器偏置电流的流水线模数转换器,实现了8~11bit和400k^40MSa/s的程控范围.提出了一种新颖的预充型开关运放,在降低功耗的同时,可以使运算放大器快速开启.通过采用改进的电流调制功耗缩放技术、新颖的开关运放技术、采样保持电路消去技术和动态比较器,大大降低了电路的功耗.电路设计采用1.8V 1P6M0.18μm CMOS工艺,仿真结果表明:在11bit,40MSa/s性能条件下,输入信号为19.02MHz时,无杂散动态范围(SFDR)为81dB,信噪失真比(SNDR)为67dB,功耗为29mW. A conversion-precision and sampling-rate programmable pipeline analog-to-digital converter （ADC） ,without adjusting the bias current of operational amplifiers,is presented in this paper. This ADC achieves a conversion-precision of 8 to llbits and a sam- piing-rate from 400k to 40MSa/s. To increase the power-on speed and reduce the power consumption,a novel pre-charged switched operational amplifier is proposed. The power can be significantly reduced by adopting an improved current modulated power scaling （CMPS） technique,the proposed switched operational amplifier, a SHA-less technique, and a dynamic comparator. The ADC is de- signed in a 1.8V 1P6M 0.18μm CMOS process. Simulation results indicate that the ADC exhibits a spurious free dynamic range （SFDR） of 81dB and a signal-to-noise and distortion ratio （SNDR） of 67dB. Programmed at llbits and 40MSa/s,the ADC consumes 29mW when a 19.02MHz sine signal is fed-in.
作者 魏琦 殷秀梅 杨斌 杨华中
机构地区 清华大学电子工程系电路与系统教研室
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第5期1010-1015,共6页 半导体学报（英文版）
关键词 流水线 模数转换器 开关运算放大器 pipeline ADC switched operational amplifier
分类号 TN792 [电子电信—电路与系统]
  • 相关文献

参考文献12

  • 1Ahmed l,Johns D A. A 50-MSps (35mW) to 1-kSps (15μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation. IEEE J Solid-State Circuits, 2005,40 : 2446
  • 2Gulati K, Lee H S. A low-power reconfigurable analog-to-digital converter. IEEE J Solid-State Circuits, 2001,36( 11 ) : 1900
  • 3Bo Xia, Valdes-Garcia A. A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802. lib/Bluetooth receiver. IEEE J Solid-State Circuits,2006,41(3) :530
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  • 5Hernes B, Briskemyr A,Andersen T N,et al. A 1.2V 220MS/s 10bit pipeline ADC implemented in 0.13μm digital CMOS. IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2004:256
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同被引文献16

  • 1Andersen T N,Hernes B,Briskemyr A,et al.A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS.IEEE Journal of Solid-State Circuits,2005,40(7):1506-1513.
  • 2Ray S,Song B S.A 13-b linear,40-MS/s pipelined ADC with self-configured capacitor matching.IEEE Journal of Solid-State Circuits,2007,42(3):463-474.
  • 3Iroaga E,Murmann,B.A 12-bit 75-MS/s pipelined ADC using incomplete settling.IEEE Journal of Solid-State Circuits,2007,42(4):748-756.
  • 4Ryu S T,Ray S,Song,B S.A 14-b linear capacitor self-trimming pipelined ADC.IEEE Journal of Solid-State Circuits,2004,39(11):2046-2051.
  • 5Wang X,Hurst P J,Lewis S H.A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration.IEEE Journal of Solid-State Circuits,2004,39(11):1799-1808.
  • 6Grace C R,Hurst P J,Lewis S H.A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration.IEEE Journal of Solid-State Circuits,2005,40(5):1038-1046.
  • 7Daito M,Matsui H,Ueda M,et al.A 14-bit 20-MS/s pipelined ADC with digital distortion calibration.IEEE Journal of Solid-State Circuits,2006,41(11):2417-2423.
  • 8Ahmed I,Johns D A.A 50-MSps (35 mW) to 1-kSps (15 μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation.IEEE Journal of Solid-State Circuits,2005,40(12):2446-2455.
  • 9Chiu Y,Gray P R,Nikolic B.A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR.IEEE Journal of Solid-State Circuits,2004,39(12):2139-2151.
  • 10Ryu S T,Song B S,Bacrania K.A 10-bit 50-MS/s pipelined ADC with opamp current reuse.IEEE Journal of Solid-State Circuits,2007,42(3):475-485.

引证文献1

Journal of Semiconductors
2008年 第5期

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