期刊文献+

基于精简标准单元库的OPC复用技术

OPC Reuse Based on a Reduced Standard Cell Library
下载PDF
导出
摘要 提出了一种对标准单元的光学邻近效应校正结果进行复用的方法,并通过将传统标准单元中的所有核心逻辑通过反相器和二选一多路选择器的组合来实现,得到了一套可制造性强的精简标准单元库,从而使OPC复用技术得以有效实施,并将在很大程度上提高芯片生产效率和降低掩模数据存储量.精简标准单元库中单元的电气仿真结果表明其在面积、速度、功耗方面与传统标准单元库相比性能损失很小. This paper presents a method for reusing the results of standard-cell-based OPCs. For this purpose,a reduced standard cell library composed of an inverter and MUX2 is constructed to realize the core logic of a traditional standard cell library. This library is manufacturing-friendly, and the reuse of its OPC results can improve the efficiency of chip manufacturing greatly and highly reduce the need for large storage. The electrical simulation results of the library also show that its increase in area,delay,and power is minor compared with traditional standard cell libraries.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第5期1016-1021,共6页 半导体学报(英文版)
关键词 精简标准单元库 OPC复用 可制造性设计 电气仿真 reduced standard cell library OPC reuse design for manufacturability electrical simulation
  • 相关文献

参考文献12

  • 1Gennari F E. Linking TCAD and EDA through pattern matching. PhD Thesis in EECS, University of California, Berkeley, 2004
  • 2Gupta P, Heng F L,Lavin M A. Merits of cellwise model-based OPC. Proceedings of the SPIE, 2004,5379 : 182
  • 3Wang Xin, Pillof M, Tang Hongbo, et al. Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration. Proceedings of the SPIE,2005,5756 ~ 361
  • 4Pawlowski D M, Deng Liang, Wong M D F. Fast and accurate OPC for standard-cell layouts. Proceedings of the 12th Asia and South Pacific Design Automation Conference,2007:7
  • 5Maly W,Lin Y W,Marek-Sadowska M. OPC-free and minimally irregular IC design style. Proceedings of the 44th Design Automation Conference,2007:954
  • 6Wong A K K, Resolution enhancement techniques in optical lithography. Bellingham : SPIE Press, 2001
  • 7Tong K Y,Kheterpal V,Rovner V,et al. Regular logic fabrics for a via patterned gate array (VPGA). Proceedings of the IEEE 2003 Custom Integrated Circuits Conference,2003:53
  • 8Kheterpal V,Rovner V, Hersan T G, et al. Design methodology for IC manufacturability based on regular logic-bricks. Proceedings of the 42nd Design Automation Conference,2005:353
  • 9Ran Yajun, Marek-Sadowska M. Via-configurable routing architectures and fast design mappability estimation for regular fabrics. Proceedings of the 2005 IEEE/ACM International Conference on Computer-Aided Design ,2005:25
  • 10Ran Yajun, Marek-Sadowska M. Designing via-configurable logic blocks for regular fabric. IEEE Trans Very Large Scale Integration (VLSI) Systems,2006,14(1) :1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部