高速串行通信中的自适应判决反馈均衡器设计

An Adaptive Decision Feedback Equalizer for High Speed Serial Communication

介绍了用于串行通信中的自适应判决反馈均衡器系统以及电路设计.论述了高速串行通信系统设计中的关键要点.从系统设计的角度阐明了串行通信系统中均衡器的重要性.介绍了一个基于半速率采样系统的自适应判决反馈均衡器,它采用5条反馈回路消除信号的码间串扰和直流失调.电路设计采用 TSMC 90 nmCMOS 工艺实现,仿真结果表明,设计的自适应判决反馈均衡器可以恢复出最高达6.25 Gb/s 的串行数据,并且在电源电压1.2V 情况下,对整个收发器仅增加约14mW 的功耗.

An adaptive Decision Feed-back Equalizer （DFE） based on half-rate clock used in the serial communication is described. At first, introduce the system design key in the communication. Then, the DFE is described. It has 5 feedback taps for canceling inter-symbol interference （ISI） and for canceling dc offset. The design is implemented in TSMC 90 nm CMOS process and power supply is 1.2 V. Simulation results show that the DFE can recover 6.25 Gb/s data over a high-loss backplane channel, while the total power dissipation overhead is about 14 mW.