宽带数字接收机的高效FPGA设计

Efficient Design of Wideband Digital Receiver on FPGA

在FPGA中实现了一种高效的宽带数字接收机,采用坐标旋转数字计算机算法实时产生数控振荡器数据,提高了接收机设计的灵活性。二次变频的接收机结构和四倍抽取的多相滤波结构减少了接收机的运算量,降低了接收机的资源消耗。FPGA中的仿真结果证明了该方法的高效性和实用性。

A method to design wideband digital receiver on filed programmable gates array （FPGA） is proposed in this paper. The coordinate rotation digital computer （CORDIC） algorithm is employed to generate real time numerically controlled oscillator （NCO） data. Double frequency conversion, quarter decimation and polyphase filters further enhance the system performance. The proposed receiver is more flexible, less computation and less resource consumption. Design example and simulation results are shown to testify the validities and feasibilities.