DVI输出图像选区截取的FPGA实现

Implemention of Regional Interception for DVI Outputting Image Based on FPGA

介绍了数字视频接口(DVI)解码芯片SiI1161的功能及其外围配置、DDC通道及编辑EDID的方法,阐述了在FPGA中依据VESA Monitor Timing标准,利用有限状态机进行数据截取的过程,经验证DVI输出的选区图像达到了在LED大屏幕上实时显示的效果。

The functions and configurations of Digital Video Interface（DVI） receiver SiI1161, together with the methods of DDC channel and editing Extended Display Identification Data（EDID） are described. The process of data interception in FPGA which is based on VESA_Monitor Timing standard and uses finite state machine is exhausted. Through verifying, the outputting image of DVI has achieved the real-time display effect of LED large screen.