基于FPGA的中值滤波算法研究与硬件设计

Research and Hardware Design of Median Filtering Algorithms Base on FPGA

本文以FPGA为平台,使用VHDL硬件描述语言设计并实现了中值滤波图像处理算法。在设计过程中,通过改进算法和优化结构,在合理地利用硬件资源的基础上,有效地挖掘出算法内在的并行性,采用流水线结构优化算法,提高了处理速度。文中提出了一种快速中值滤波算法,可以大大节省硬件资源,同时提高了处理速度。

Based on FPGA platform, with the use of VHDL hardware description language to design and implementation of median tittering algorithm for image processing. In the design process, through improved algorithms and optimizing the structure, the rational use of hardware resources, under the condition effectively tapping algorithm inherent parallelism, pipelining used structural optimization algorithm, enhanced processing speed. This paper presents a fast median filtering algorithm, which can greatly save hardware resources and improve the processing speed.