基于标志压缩的低功耗指令cache设计

Tag Compression for Low Power in Instruction Caches

引入了一种基于标志压缩的降低指令cache功耗的方法.对优化后的微处理器功耗分析结果表明,如果对标志压缩缓冲区的大小适当设定,与优化前的情况相比,指令cache的功耗可降低64%.

This paper introduces an approach for reducing instruction cache power based on the operation of the tag compression registers added in the cache system. The power savings show that, when the size of the tag compression registers is properly fixed, the average saving on the power corusumption of the instruction cache could be up to 64% compared with the traditional instruction cache structure.