基于NEDA算法的二维DCT硬件加速器的设计实现

A New Distributed Arithmetic Architecture Design for 2D-DCT Accelerator

应用二维DCT的图像压缩系统,DCT的运算量较大,为了突破该瓶颈,设计了基于NEDA算法的DCT硬件加速器,该设计方案采用移位相加代替乘法运算,并用RAM代替ROM,有效地节省了硬件资源.给出了Verilog仿真结果,结果表明该加速器可以在使用资源非常少的情况下,正确地实现二维DCT运算,适合于各种视频图像压缩方面的应用.

For an image compression system using a two-dimensional DCT, the computation of DCF is usually large enough to become the bottleneck. In order to break through the bottleneck, we present the design for DCT hardware accelerator based on NEDA algorithm. In the full paper, we explain the design in detail. We make use of adder and shifter replacing multiplication and use ROM instead of RAM, which saves the hardware resources effectively. From the Verilog simulation results, we can see that this accelerator design implements the two-dimensional DCT correctly using very few logic dements, and it can be used in a variety of video compression applications.