龙芯2E多处理器芯片组的设计与实现

Design and implementation of multi-processor chipset based on Godson 2E CPU

提出了一种面向高性能计算机的多处理器芯片组的设计,其主要特点是支持多处理器通过芯片组和交换芯片两级互连,全局地址空间和多处理器同步支持。给出了芯片组的组成结构、设计原则和关键技术,设计并实现了基于龙芯2E处理器的多处理器芯片组。目前,已采用FPGA平台对该芯片组进行验证和测试,以该芯片组为核心的四处理器原型系统完成B IOS引导和操作系统运行,经过实测处理器的访问请求通过芯片组延迟小于0.5μs,芯片组内处理器通信带宽达到500 Mbps。

This paper introduced the design of a multi-processor chipset for high performance computer, whose features were the two-layer interconnection by chipset and router, global address space （GAS） and the support for synchronization. It described the architecture, design principles and key techniques of the multi-processor chipset ,and the FPGA implementation of the chipset based on Godson 2E CPU was presented. The 4-CPU prototype system could run Linux operating system. The expe -riment shows that the latency across the chipset is less than 0. 5 μs and the bandwidth between two CPUs is up to 500 Mbps.