A率μ率转换器的ASIC设计

ASIC Design of A-Low and μ_Low Comverter

根据程控交换原理和A率、μ率压扩编码原理,提出一种具有A率μ率转换器的ASIC实现方案。详细给出了A率μ率转换器的电路结构,以及用查表法实现A率μ率转换器的具体方法。该电路结构简单,易于设计,适合用可编程器件(FPGA)实现。用Verilog HDL语言完成了电路设计,逻辑验证,用Xilinx的FPGA XC4006EPC84-4实现电路,经实验测试,设计结果符合系统要求。

According to principles of digital switching system and A-low and μ-low,this paper gives an idea of ASIC design of A-low and μlow converter.The circuit structure are given in detail and using look-in-table for the converter.Using Verilog HDL to design and virificate the system,and implement the system with Xilinx FPGA XC4006EPC84-4,It is proved by hardware experiment that the performance can meet the digital switching system.The ASIC are useful in digital switching system.