高阻衬底集成电路抗闩锁效应研究

Research on Latch up Immunity in IC of High Resistance Substrate

研究用增加多子保护环的方法抑制功率集成电路的闩锁效应,首次给出环距、环宽设计与寄生闩锁触发阈值的数量关系,并比较了不同结深的工序作为多子环的效果。对于确定的设计规则,还比较了不同电阻率衬底材料的CMOS单元中的闩锁效应,结果表明合理设计可以有效地改善高阻衬底的寄生闩锁效应,仿真结果验证了正确性。

A majority cartier guarding was used to improve latch up immunity in power IC. The relation between the location and width of the guarding and the triggering voltage were proposed, and the efficiency of that used different processes as majority cartier guarding were compared. To a fixed rule, the latch up phenomena in CMOS devices of different resistance Si materials were also compared. The results show that reasonable design can improve latch up immunity in high resistance substrate, the validity is proved in simulations.