ADPLL数学建模与设计实现

Mathematics Modeling and Design Implement of ADPLL

全数字锁相环（ADPLL）与混合信号锁相环相比，具有功耗低、面积小、锁定时间短和易于移植等优点。提出了一种新的全数字锁相环结构，建立了该锁相环的系统级数学模型，通过Matlab仿真验证了系统的可行性，并用非线性理论证明了该系统的稳定性。并用建立的系统结构实现了ADPLL的电路版图，电路版图经0.13μm工艺流片验证，实现了输入为2-25 MHz、输出为25-500 MHz的全数字锁相环电路样品。

Compared with mixed-signal PLL, ADPLL （all digital phase locked loop） has more advantages in some aspects, such as low power, small size, less locked-time, easy to replant to other technology, and more tolerance with noise. A novel architecture of ADPLL was introduced, precise mathematical model of the ADPLL was built with Matlab. The simulation result proves the feasibility of this system. The ADPLL system was taped out successfully in 0.13 μm technology with 2 to 25 MHz input and 25 to 500 MHz output.