VHDL语言中配置语句的使用探讨

The Discussion of The Configuraition Statement Application in VHDL Language

配置是VHDL语言的一个基本设计单元，用来为设计实体指定综合或仿真时采用的结构体。论文结合教学实际讨论了VHDL语言中配置语句的常用的三种用法：默认配置、元件配置和结构配置。论文首先论述了每种配置语句的格式，然后以数字电路中的半加器和全加器的VHDL描述为例，说明每种配置语句格式的使用方法。最后对论文内容进行归纳并得出几点结论。论文对VHDL语言教学及基于VHDL层次化电路设计都具有一定的指导意义。

Configuration is a fundamental design unit of VHDL language, which is used to allocate the structure to a design entity when it is synthesizd or simulated. Combing with teaching practice, this paper mainly discussses three common configuration in VHDL language： there are default configuraion, component configruration and structural configuration. The statement form of each configruation is discussed firstly, then the paper focuses on explaining the application of each configruation by taking the examples of the VHDL description of the half-adder and full-adder in digital circuit. After that, a summary of this paper is given and some conclusions is drawn, which can provide some helpful direction for VHDL teaching and hierarchical circuit design based on VHDL.