流水线模数转换器的一种数字校准技术

A Digital Calibration Technique of Pipelined Analog-to-Digital Converter

为了降低流水线模数转换器中数字校准电路的规模和功耗，提出了一种新的基于信号统计规律的后台数字校准技术．该技术采用自适应搜索算法和二元单调函数的幅值增量比较算法，分别对基于信号统计规律的数字校准技术中的距离估计电路和查找表进行了优化设计，减少了距离估计所需的数字电路和查找表所需的ROM空间，极大地降低了数字电路的规模和功耗．应用该校准技术实现了一个12位、采样率为4×10^7s^-1的流水线模数转换器．测试结果表明，同优化前相比，该芯片数字电路的功耗降低了93％，

To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter （ADC）, a new statistics-based background calibration technique is presented. In order to improve both the residual distance estimator circuit and the design of look up table （LUT） in binary monotonically function, an adaptive search algorithm and a magnitude incremental comparison algorithm are used in the calibration technique. The technique can reduce the digital circuits＇ scale of distance estimator and the memory of ROM of LUT. By using the technique, the power dissipation in digital circuits and the chip size are reduced significantly. The improved technique is applied in the implementation of one 12 bit 4 × 10^7 s^-1 pipelined ADC. The tested results show that power consumption of digital circuits is reduced by 93% and the memory of ROM is saved by 95%, compared with the unimproved technique. The ADC implemented in SMIC 0. 18 μm CMOS process consumes 210 mW, and occupies a chip area of 3. 3 mm×3. 7 mm.