低功耗低噪声CMOS放大器设计与优化

Design and optimize of a low power CMOS LNA

分析了两种传统的基于共源共栅结构的低噪声放大器LNA技术:实现噪声优化和输入匹配SNIM技术并在功耗约束下同时实现噪声优化和输入匹配PCSNIM技术。针对其固有不足,提出了一种新的低功耗、低噪声放大器设计方法。

This paper reviews and analyzes two reported low-noise amplifier （LNA） design techniques applied to the caseode topology based on CMOS technology, simultaneous noise and input matching （SNIM）and power-constrained simultaneous noise and input matching（PCSNIM） techniques .In order to make best use of their advantages and avoid their fundamental limitations, an improved PCSNIM LNA is proposed. The proposed monolithic LNA is implemented in SMIC＇s standard 0.13μm CMOS RF technology, which could provide noise figure of 2.2dB and gain of 14.3dB at 5.5GHz with only 3mW power consumption.