基于SRAM的FPGA的互连时延模型

A delay model for SRAM-based FPGA interconnections

本文提出现场可编程门阵列FPGA中的互连资源MOS传输管时延模型。首先从阶跃信号推导出适合50%时延的等效电阻模型,然后在斜坡输入的时候,给出斜坡输入时的时延模型,并且给出等效电容的计算方法。结果表明,本文提出的时延模型快速并且足够精确。

This paper proposes FPGA interconnection pass transistor delay model. First, the equivalent resistance delay model is presented based on 50% timing delay for the pulse input. The equivalent capacitance delay model is thereafter proposed for the slope input. The corresponding effective capacitance delay calculation method is also given. The experimental results show the efficiency and accuracy of the proposed delay model for FPGA interconnection.