摘要
提出了AVS解码系统中帧间运动补偿插值算法的一种面向FPGA/ASIC的硬件结构设计。阐述了插值过程的各功能单元的结构,给出了仿真结果及硬件规模。结果表明本文提出的结构设计支持720×576,4:2:0,30FPS的视频在54MHz最低工作频率下的实时解码,是一种适合于集成的高效并行VLSI结构设计。
A hardware architecture for implementing interpolation of motion compensation in AVS decoder system in FPGA/ASIC is proposed. The architecture of every functional unit is explained. The simulation result and the hardware scale are given. The result indicates that the proposed architecture can work with the minimal frequency of 54MHz for decoding 720×576, 4：2：0, 30FPS video frames real time. It is an efficient VLSI architecture and it is suitable for integration.
出处
《电路与系统学报》
CSCD
北大核心
2008年第3期148-152,共5页
Journal of Circuits and Systems
