期刊文献+

p^+多晶Si_(1-x)Ge_x功函数对异质结CMOS器件电学特性影响的模拟研究

Simulation Study of Effect of Work Function of p^+ Polycrystalline Si_(1-x)Ge_x on Electrical Properties of Heterojuncion CMOS
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摘要 为使垂直层叠SiGe/Si异质结CMOS器件具有匹配的阈值电压,利用二维器件模拟器MEDICI模拟分析了p+多晶Si1-xGex栅的功函数对此类器件直流与交流特性参数的影响,得出在P+多晶Si1-xGex功函数W=0.85eV,即Ge组分x=0.36时,此类器件的p-MOSFET与n-MOSFET具有匹配的阈值电压,分别为VTp=-0.215V和VTn=0.205V。为此类器件的优化设计和制备提供了理论依据。 To obtain the match threshold voltage of vertical stack SiGe/Si Heterojunction CMOS device, effects of work function of p^+ polycrystalline Si1-xGex gate on electrical properties of this device are simulated and analyzed by two-dimensional device simulator MEDICI, the results show that when work function of p^+ polycrystalline Si1-xGex ,W=0. 85 eV (x=0. 36), the match threshold voltage of p-MOSFET and n-MOSFET can be obtained,and the threshold voltage of p-MOSFET and n-MOSFET are VTp=-0. 215 V and VTn=0. 205 V, respectively. Theoretical evidence is provided for the design optimization and fabrication of this kind of device.
出处 《电子器件》 CAS 2008年第3期795-799,共5页 Chinese Journal of Electron Devices
基金 武器装备预研基金项目资助(51408061104DZ01)
关键词 异质结CMOS p^+多晶Si1-xGex栅 MEDICI模拟 功函数 Heterojunction CMOS p^+ polycrystalline Si1-xGex gate MEDICI simulation work function
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参考文献10

  • 1Yu Shaofeng,Jung Jongwan,Hoyt Judy L,et al.Strained-Si-Strained-SiGe Dual-Channel Layer Structure as CMOS Ubstrate for Single Workfunction Metal-Gate Technology[J].IEEE Electron Device Letters,2004,25(6):402-404.
  • 2Jung Jongwan,Yu Shaofeng,Lee Minjoo L,et al.Mobility Enhancement in Dual-Channel P-MOSFETs[J].IEEE Transactions on Electron Devices,2004,51(9):1424-1431.
  • 3Olsen Sarah H,O'Neill Anthony G,Chattopadhyay Sanatan,et al.Study of Single-and Dual-Channel Designs for High-Per-formance Strained-Si-SiGe n-MOSFETs[J].IEEE Transac-tions on Electron Devices,2004,51(7):1245-1253.
  • 4Sadek A,Ismall K,Armstrong M A,et al.Design of Si/SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors[J].IEEE Transactions on Electron Devices,1996,43(8):1224-1232.
  • 5Chun S K,Wang K L Effective Mass and Mobility of Holes in Strained Si1-xGex Layers on (001) Si1-xGex Subsrate[J].IEEE Transaction on Electron Devices,1992,39(9):2153-2164.
  • 6Ponomarev Youri V,Stolk Peter A,Salm Cora,et al.HighPerformance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates[J].IEEE Transactions on Electron De vices,2000,47(4):848-855.
  • 7Wong D M and Tart N G.Sealing the SiGe Channel PmetalOxide-Seniconductor Field Effect Transistor:The Case for p+SiGe Gates[J].Vac.Sci Technol A,2000,18(2):783-785.
  • 8Ismail K,Nelson S E Electron Transport Properties of Si/SiGe Heterostructures:Measurements and Device Implications[J].Applied Physics Letter,1993,63(8):660-662.
  • 9Briggs P J,Walker Alison B,Herbert D C.Calculation of Hole Mobilities in Relaxed and Strained SiGe by Monte Carlo Simulation[J].Semiconductor Science and Technology,1998,13(4):680-691.
  • 10Hellberg P E,Zhang S L,Petersson C S.Work Function of Boron-Doped Polycrystalline Si1-xGex Films[J].IEEE Elec-tron Devices Letters,1997,18(9):456-458.

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