低电压高速CMOS电流模线性鉴相器的设计

Design of Linear Phase Detectors with Low-Voltage High-Speed CMOS CML Circuits

在高速时钟和数据恢复电路(CDR)中一般采用高数率比线性鉴相器(LPD)来降低鉴相器(PD)和压控振荡器(VCO)的工作频率。从电路结构的复杂度、芯片面积以及功耗三方面,对三种不同速率比LPD电路进行了分析比较;针对2.5Gbit/s CDR电路的具体应用,分别设计了半数率比和1/4数率比LPD,均通过了功能仿真;最后比较仿真结果,在2.5Gbit/s应用下,半数率比结构是合理的选择。电路设计采用TSMC0.18μm CMOS混合信号工艺,LPD电路均采用低电压高速电流模逻辑(CML)实现。

Linear phase detectors（LPD are commonly used in high-speed clock and data recovery（CDR circuits to achieve a high data-rate with lower operating frequency of both phase-detector（PD and voltage-controlled oscillator （VCO. Three different rate LPDs are discussed and compared with complexity of circuit structure, layout area and power consumption. Also, a half-rate LPD and a 1/4-rate LPD are proposed for the design of a 2. 5 Gbit/s CDR circuit. Both of them are satisfactory to the function simulation. According to the simulation results, the half-rate structure is better for the 2. 5 Gbit/s application. All of the LPD discussed or designed are realized by low-voltage current-mode logic （CML） gates for its high-speed performance.