一种应用于8B/10B编码串并转换电路的低功耗LVDS接收器设计(英文)

Low-Power LVDS Receiver with Equalization for 8B/10B SerDes

低电压差分信号(LVDS)是串并转换电路(SerDes)的一种主流接口技术。本文设计并实现了一种适合于8B/10B编码串并转换电路的LVDS接收器(Receiver)。本设计的指标完全兼容IEEEStd1593.3-1996标准。它支持最大0.05V至2.35V的共模电平输入范围,最小100mV的差模输入,能够在至少40英寸FR4带状线上达到1.6Gb/s的接收速率,平均功耗3mW。电路设计基于0.18μm1.8V/3.3V CMOS工艺,同时采用了3.3V器件和1.8V器件。

LVDS （Low-Voltage Differential Signals） is one of the mainstream techniques for SerDes （serializer/deserializer） I/Os. This paper presents the design and implementation of a LVDS receiver for 8B/10B SerDes. The receiver is fully compatible with IEEE Std 1596.3-1996 standard, and supports input common-mode range of 0.05 V to 2. 35 V and minimum input differential signal of 100 mV. It can operate at up to 1.6 Gb/s over at least 40-inch FR4 stripline with equalization and has only 3 mW power consumption. The design is based on 0. 18μm 1.8 V/3.3 V CMOS technology using both thick （3.3 V） and thin （1.8 V） gate oxide devices.