GaN紫外焦平面CTIA结构读出电路小面积设计及仿真

Small Pixel Area Design of GaN UV FPA ROIC with CTIA Structure and Simulation

随着GaN紫外焦平面的发展,焦平面的阵列规模越来越大,单元探测器的面积越来越小,对GaN紫外焦平面的读出电路进行设计,实现读出电路单元面积为37μm×37μm,阵列规模为8×8元。本设计采用电容反馈互阻抗放大器(CITA)结构作为输入级,列共用方式的采样保持电路,源级跟随器作为输出级,用移位寄存器来控制行、列选通并控制电路工作的时序。本文的整个电路设计基于Cadence设计平台,对电路进行了Spectre仿真,面阵的工作状况良好,保持良好的线性。

With the development of the GaN UV FPAs, there is a lot more limitation placed on the area used by the ROIC （Read-Out Integrated Circuit） and the power consumption. We design ROIC with CTIA as the input grade. To reduce the area of the layout, we use one-stage OP-AMP in the ROIC, and the sample and hold circuit shared by pixels in a column is also applied instead of sample and hold circuit in every pixel. The simulation results produced by spectre are shown, attached by working scheme. The array has 8 x 8 pixels and each one＇ s area is 37 μm × 37 μm.