高吞吐量低存储量的LDPC码译码器FPGA实现

FPGA implementation of a high-throughput memory-efficient LDPC decoder

针对规则(r,c)-LDPC码,设计了一种基于Turbo结构的FPGA译码实现算法,采用多路并行译单帧数据,多帧并行译码的结构,具有收敛速度快和存储量低的特点.为实现多路并行译单帧数据,首先将LDPC码划分成几个超码,并对每个超码内的单校验码采用并行BCJR算法.同时,为简化并行BCJR译码时的内部结构和控制单元的复杂度,提出一种修正的分圆陪集构造方法.在具体实现中,采用了3帧并行译码的结构来进一步提高吞吐量.对一个码长为1 600,规则(3,5)-LDPC码,用Altera公司的StratixEP1S25 FPGA芯片设计了译码器,在主频40 MHz条件下采用20次迭代,可使吞吐量达50 Mbit/s.

Based on the Turbo-decoding algorithm, a high-throughput memory-efficient decoder is proposed for a class of regular （r, c）-LDPC （low-density parity-check） codes. Compared to the traditional sum-product decoding algorithm, the Turbo-decoding algorithm decodes several packets in parallel, each of which is decoded by a parallel structure, resulting in faster convergence behavior and fewer memories. To decode a packet with a parallel structure, the LDC code is first divided into several super-codes. Then, each super-code is decoded by the parallel BCJR algorithm. To further simplify the inter-structure and the complexity, a modified coset algorithm is also proposed. An FPGA chip containing 15 parallel decoders for a regular （r, c）-LDPC code of length 1 600 has been developed based on the Altera Stratix EP1S25 FPGA device, which decodes 3 packets in parallel and can achieve a throughput of 50 Mbit/s with 20 decoding iterations.