带定向通路的十读六写寄存器文件全定制设计

Custom Design of a Register File with 10R/6W Ports and the Forwarding Path

本文介绍了一个带定向通路的十读六写寄存器文件在0.18μmCMOS工艺下的全定制设计,与基于标准单元半定制寄存器文件相比,面积和功耗都缩小了近一半,延迟从2.34ns减小为1.2ns。在建立视图时,通过采用伪时序建模的方法大大减小了建模的工作量。该设计已运用于YHFT系列DSP芯片中。

In this paper, we discuss how to custom design a register file with 10R/6W ports and the forwarding path in the 0. 18μm CMOS technology. Compared with the half-customed register file based on standard cells, the area and power dissipation are reduced about 1/2 and the delay reduced from 2. 34ns to 1.2ns. In order to reduce workload, we use a pseudo timing model. This design has been applied to YHFT-DSP chips.