面向高性能计算的流VLIW编译技术研究

On the Stream VLIW Compilation Techniques for High Performance Computing

本文基于斯坦福大学设计的KernelC编译器ISCD[1],针对64位流处理器体系结构,设计实现了其核心VLIW编译器,并针对高性能计算应用需求进行优化,实现了分布式寄存器负载均衡和指令自动合并技术。实验结果表明,该编译器能够很好地开发程序中的并行性,具有较高的效率。

Based on the KernelC compiler ISCD designed by Stanford University, according to the 64-bit Stream Processor Architecture, this paper designs and implements a Kernel-level VLIW compiler. To make special optimization for the application in high performance computing, we implement the techniques of distributed register file workload balancing and automatic instruction merging. Experiments show that the compiler can exploit the parallelism in programs effectively.