800MSPS FADC数据采样系统的研制

An 800MSPS FADC Data Sampling System

本文开发了一种基于MAX105 800MSPS 6bit FADC和FPGA的高速数据采样系统。FADC的输出通过FPGA中的串并转换电路降低到100MHz,便于后续数据处理和传输。FPGA还实现了数据缓存、自甄别触发以及压缩和时间信息获取等功能。经过压缩和缓存的数据由TELL1采集并传送计算机,最大数据带宽可达4Gbps。

This paper discuss a 800MSPS data acquisition system using MAX105 device. The system achieves a sampling rate of 800MSPS, and converts the high speed LVDS signals to low speed LVTTL signals using FPGA. And the FPGA implements the amplitude discrimination and obtains time information. Then FPGA sends the data to the TELL1 readout board. The TELL1 board sends the data to the Gigabit Ethernet with the Gigabit Ethernet link.