IA-64的并行架构及其寄存器文件

Parallel Infrastructure of IA-64 and Its Register File

同时多线程能在同一时钟周期执行不同线程的指令,并且指令级并行和线程级并行。显式并行指令计算关注于编译器和硬件的相互协作。寄存器文件的设计在高性能处理器设计中十分重要,寄存器栈和寄存器栈引擎是提高其性能的重要手段。该文设计和实现一套并行环境,其中包括并行编译器OpenUH和基于IA-64的同时多线程体系结构EDSMT,实验表明,该并行架构适用于大多数并行应用,针对NAS的并行测试程序,该架构相对于SMTSIM平均有12.48%的性能提升。

Simultaneous Multithreading（SMT） processors execute instructions from different threads in the same cycle,which has the unique ability to exploit ILP and TLP simultaneously.Explicitly Parallel Instruction Computing（EPIC） emphasizes importance of the synergy between compiler and hardware.Register file design is very important in high performance processor design.Register stack and register stack engine are effective ways to improve performance.This paper presents efforts to design and implement a parallel environment,which includes an optimizing,portable parallel compiler OpenUH and SMT architecture EDSMT based on IA-64.Meanwhile,its register file mechanism is carefully designed.Experimental results show the infrastructure is suitable for parallel applications and the IPC increment over SMTSIM is 12.48% in average using the NAS parallel benchmarks.