基于FPGA的H.264去块滤波系统的优化设计

Optimized Design of H.264 Deblocking Filter System Based on FPGA

提出一种H.264去块滤波系统的优化设计方法。通过合理设计流水线级数提高并行性,适当增加内部SRAM来提高系统速度和总线利用率,使用一种层次化的有限状态机设计方法,实现对数据流的精确控制并且有效降低硬件实现复杂度。基于FPGA的验证结果显示在最坏情况下滤波每个宏块平均只需220个时钟,比原有方案快10个时钟以上。

This paper presents an optimized deblocking filter method.The design improves the speed of system and efficiency of bus via a pipeline with suitable stages,enhancing the parallelism,and using some local SRAM.The paper presents a hierarchy Finite State Machine（FSM） design method which can control the data path precisely and reduce the complexity of hardware.The Field Programmable Gate Array（FPGA） simulation displays that filtering one Macro Block（MB） only costs 220 cycles in the worst case.