14位20MS／sCMOS流水线A／D转换器

A 14-Bit 20 MS/s CMOS Pipelined A/D Converter

介绍了一种14位20MS/sCMOS流水线结构A/D转换器的设计。采用以内建晶体管失配设置阈值电压的差分动态比较器,省去了1.5位流水线结构所需的±0.25VR两个参考电平;采用折叠增益自举运算放大器,获得了98dB的增益和900MHz的单位增益带宽,基本消除了运放有限增益误差的影响;采用冗余编码和数字校正技术,降低了对比较器失调的敏感性,避免了余差电压超限引起的误差。电路采用0.18μmCMOS工艺,3.3V电源电压。仿真中,对频率1MHz、峰值1V的正弦输入信号的转换结果为:SNDR85.6dB,ENOB13.92位,SFDR96.3dB。

14-bit 20 MS/s CMOS pipelined A/D converter was presented. Differential dynamic comparators were used, which set the threshold voltage by using mismatch of inter-transistors. Two reference voltages, ±0. 25 VR, were eliminated, which were necessary for 1. 5-bit pipeline A/D converter. Folded gain-boost cascade operational amplifier was used to actualize gain of 98 dB and GBW of 900 MHz and reduce the finite gain error. Redundancy coding and digital correction technique were also used to reduce circuit sensitivity to dynamic comparator and to reduce errors due to residue voltage exceeding the limitation. The design was implemented in 0. 18μm standard CMOS technology with 3. 3 V supply voltage. A 1 MHz, 1 V sine signal was sampled by a 20 MHz sampling signal. Simulation results showed that an SNDR of 85.6 dB, an ENOB of 13.92 bits, and an SFDR of 96. 3 dB were achieved.