基于FPGA的SpaceWire接口容错设计与评估

The Evaluation of an SpaceWire Interface Fault Tolerant Design Basing on FPGA

SpaceWire是一种面向航天应用的高速通信标准,对其做容错设计对于系统的可靠性具有重要意义。本文的工作是在分析SpaceWire协议错误处理机制的基础上,对基本的SpaceWire接口电路在逻辑层做了三方面的容错设计:一是FIFO模块的纠一检二汉明编码设计;二是状态机状态编码的容错设计考虑;三是寄存器的三模冗余设计。以上设计都在Xilinx的FPGA中实现和验证,并对容错设计对性能和面积的影响做出了分析和比较。

In this work,three logical fault tolerant techniques are applied on a SpaceWire interface circuit after analysis of SpaceWire error handling mechanism,as the reliability is of great importance to this communication standard which is specially presented for spacecraft onboard communication.The techniques are including：1.An implementation of SED-DED Hamming encoding on module FIFO,2.Fault tolerant design of state machine,3.The implementation of TMR registers.Those techniques are all implemented on Xilinx FPGA with evaluation and analysis of penalty of performance and area.