流水并行1-D FFT地址映射算法

Dedicated memory accessing for pipelined-parallel 1D FFT

讨论了2个流水蝶形单元并行的地址映射算法.由于FFT级间数据读写关系复杂,实现每次并行执行2个蝶式运算的地址产生非常复杂.通过对基2数据流图的改造,将存储器分为2个存储体,各级每个蝶式运算的1对操作数位于同一存储体,并行执行的2对操作数位于不同存储体相同地址,计算结果按原址写回,同时每次计算所需的2个旋转因子地址间存在一定关系,因而可用1个地址产生单元,实现2条流水线并行所需的操作数及旋转因子的并行访问.本地址产生单元易于实现,资源需求少、延时较小,且可使蝶式计算循环次数减少一半.

A hardware oriented memory accessing algorithm for two parallel butterflies is presented. The proposed algorithm using two modules of dual-port memory allows simultaneously accessing all the four input data of the pair of butterflies in processing without any conflicts. And there needs no multiplex in data address generator to choose memory modules. Moreover, at any processing cycle, only one twiddle factor is read to meet the needs of the two parallel butterflies Lecause of the relationship between them. As a result, this algorithm has less hardware complexity and less delay than some previous similar methods. With two pipelined butterflies processing simultaneously, the system designed makes that the number of butterfly eycles reduces to half.