基于布尔可满足性的层次化通路时延故障测试

Boolean Satisfiability Based Hierarchical Path Delay Fault Test

针对现代VLSI电路趋向于层次化的设计,本文提出了基于布尔可满足性的层次化通路时延故障测试方法,采用面向模块级的增量布尔可满足性合取范式的提取,从高到低层次化实现了关键通路的判别及子式生成。利用电路的时延测试条件蕴涵并转化为相应的约束子句,有利于将冲突尽早提前,以减少搜索空间。通过将已有的判别模块储存起来,作为学习子句,避免重复判别,极大的加快了子式的提取且降低了求解的规模和难度。仿真结果表明本文方案具有测试时间短、效率高,特别适合于具有模块化、规则化结构的层次化设计电路。

A satisfiability （SAT）-based path delay test scheme is proposed for modem VLSI hierarchical circuit, which exploits the merits of incremental satisfiability conjunctive normal form （CNF） clause extraction for modular combinational circuits. The selection of critical paths and the extraction of clauses are achieved from high to low level by exploiting the hierarchical structure. What＇s more, each implication is converted into a clause and the search is pruned as early as possible by encouraging conflicts. During the process, some conflicts and clauses for previous regular segments are stored and can be reused to avoid repetition. Simulation results demonstrate that compared with previous schemes, this scheme can obtain much performance improvement on speed and efficiency, which is suitable to hierarchical circuit with modular and regular structure.