期刊文献+

低功耗互补传输门绝热逻辑和时序电路的设计 被引量:1

Low-power Complementary Pass-transistor Adiabatic Logic and Sequential Circuits
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摘要 研究了采用二相非交叠功率时钟的绝热触发器及时序电路的设计,介绍了采用二相无交叠功率时钟的互补传输门绝热逻辑(CPAL)电路,并分析了其工作原理.该电路利用nMOS管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗,且CPAL能耗几乎与工作频率无关.提出了性能良好的低功耗绝热D、T和JK触发器,并与其他几种绝热触发器进行功耗比较,给出了绝热时序电路的一般设计方法,并作为实例采用应用绝热D触发器设计了十进制计数器.SPICE程序模拟表明:设计的电路具有正确的逻辑功能及低功耗的优点. We present a complementary pass-transistor adiabatic logic (CPAL) for low-power design, which is driven by two-phase AC power supply. The bootstrapped nMOS switch is employed to eliminate non-adiabatic loss on output loads. Its energy dissipation is in less dependency on power-clock frequency. The adiabatic D, T and JK flip-flops are proposed. A synthesis method for adiabatic synchronous sequential circuits is proposed. A practical sequential system based on the proposed adiabatic D flip-flop is verified. SPICE simulations demonstrate that the designed circuits have correct logic function and considerable power saving.
出处 《宁波大学学报(理工版)》 CAS 2008年第2期195-200,共6页 Journal of Ningbo University:Natural Science and Engineering Edition
基金 浙江省自然科学基金(Y104327) 浙江省教育厅项目(20070981)
关键词 低功耗技术 能量恢复 绝热触发器 时序逻辑 CPL电路 low-power energy recovery adiabatic flip-flop sequential circuit complementary pass-transistor logic
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参考文献11

  • 1Rabaey J M, Pedram M. Low power design methodologies[M]. Boston: Kluwer Academic Press, 1996.
  • 2Lim J, Kim D G, Chae S I. A 16-bit Carrylookahead adder using reversible energy recovery logic for Ultralowenergy systems[J]. IEEE J of Sol Sta Circ, 1999, 34(6): 898-903.
  • 3Moon Y, Jeong D K. An efficient charge recovery logic circuit [J]. IEEE J Sol Sta Circ, 1996, 31(4):514-522.
  • 4Kamer A, Denker J S, Flower B, et al. Second-order adiabatic computation with 2N-2P and 2N-2N2P logic circuits[C]//Proc of the International Symposium on Low Power Design. Canada: Dana Point, 1995:191-196.
  • 5Oklobdzija V C, Maksimovic D, Lin F. Pass-transistoradiabatic logic using single power-clock supply[J]. IEEE Trans Circuits and Systems II: Analog and Digital Signal Processing, 1997; 44( 10):842-846.
  • 6Liu F, and Lau K T. Pass-transistor adiabatic logic with NMOS pull-down configuration[J]. Electronics Letters, 1998, 34(8):739-741.
  • 7胡建平,岑理章,刘晓.A new type of Low-poweradiabatic circuit with complementary pass-transistor logic [C]//5th International Conference on ASIC Proceeding.中国:北京,2003:1235-1238.
  • 8胡建平,邬杨波,张卫强.Complementary Pass-Transistor Adiabatic Logic Circuit Using Three-Phase Power Supply[J].Journal of Semiconductors,2004,25(8):918-924. 被引量:1
  • 9Rabaey J M. Digital integrated circuits: a design perspective[M]. New York: Prentice Hall, 1996.
  • 10Maksimovic D, Oklobdzija V G, Nikolic B, et al. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply[J]. IEEE Trans Very Large Scale Integration Systems, 2000, 8(4):460-463.

二级参考文献10

  • 1Lim J,Kim D G,Chae S I. A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. IEEE J Solid-State Circuits,1999,34(6): 898
  • 2Maksimovic D,Oklobdzija V G. Integrated power clock generators for low energy logic. Proc IEEE Power Electronics Specialists Conference, 1995: 61
  • 3Moon Y, Jeong D K. An efficient charge recovery logic circuit. IEEE J Solid-State Circuits, 1996,31 (4): 514
  • 4Kramer A, Denker J S, Flower B, et al. 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. Proc of the International Symposium on Low Power Electronics and Design, Dana Point, 1995:191
  • 5Vetuli A,Pascoli S D,Reyneri L M. Positive feedback in adiabatic logic. Electron Lett, 1996,32(20): 1867
  • 6Kim C, Yoo S M, Kang S. Low power adiabatic computing with NMOS energy recovery logic. Electron Lett, 2000, 36(16):1349
  • 7Lim J,Kim D G,Chae S I. nMOS reversible energy recovery logic for ultra-low-energy applications. IEEE J Solid-State Circuits, 2000,35 (6): 865
  • 8Rabaey J M. Digital integrated circuits: a design perspective.New York: Prentice Hall,1996:221
  • 9李晓民,仇玉林,陈潮枢.低电压Charge-Recovery逻辑电路的设计[J].Journal of Semiconductors,2001,22(10):1352-1356. 被引量:8
  • 10戴宏宇,张盛,周润德.能量回收电路的功耗优化方法[J].Journal of Semiconductors,2002,23(9):996-1000. 被引量:2

同被引文献13

  • 1严晓浪,郑飞君,葛海通,杨军.结合二叉判决图和布尔可满足性的等价性验证算法[J].电子学报,2004,32(8):1233-1235. 被引量:8
  • 2卢永江,竺红卫,严晓浪,葛海通.利用改善的静态隐含策略加速等价性验证[J].电路与系统学报,2005,10(3):47-51. 被引量:3
  • 3卢永江,严晓浪,葛海通,杨军.结合无依赖性割集和量化的等价性验证[J].计算机辅助设计与图形学学报,2005,17(10):2215-2219. 被引量:2
  • 4郑飞君,严晓浪,葛海通,杨军,卢永江.使用输出分组和电路可满足性的等价性验证算法[J].计算机辅助设计与图形学学报,2005,17(11):2484-2488. 被引量:3
  • 5Hira M,Sarkar D.Verification of tempura specification of sequential circuits[J].IEEE Transactions on Computeraided Design of Integrated Circuits and Systems,1997,16(4):362-375.
  • 6Burch J R,Clarke E M,Mcmillan K L.Sequential circuit verification using symbolic model checking[C] //Design Automation Conefernce,1990 Proceedings 27th ACM/IEEE,1990:46-51.
  • 7Jerry R.Clarke E M,David E,et al.Symbolic model checking for sequential circuit verification[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,1994,13(4):401-424.
  • 8Eijk C A J.Sequential equivalence checking based on structural similarities[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2000,19(7):814-819.
  • 9Eijk C A J V Sequential equivalence checking without state space traversal[C] //Proceedings of the Conference on Design,Automation and Test in Europe.Washington DC,IEEE Computer Society,1998:618-623.
  • 10Ng K,Prasad M R,Mukherjee R,e al.Solving the latch mapping problem in an industrial setting[C] //Proceedings of the 40th Design Automation Conference.NewYork:ACM Press.2003:442-447.

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