基于演化硬件的容错系统设计技术研究

On Design Technology of Fault-tolerant System Based on Evolvable Hardware

提出了一种基于演化硬件的N模异构冗余容错系统设计方法.首先,改进厂一种多目标进化算法,利用改进的优化算法来设计多模冗余系统目标数字电路;然后,提出了多模数字电路设计的异构评价策略,以用于N模异构电路的优化设计;最后,将设计的异构数字电路用于组成N模冗余容错系统,以提高容错系统的可靠性.对单目标与多目标设计电路、同构与异构冗余电路的容错性能进行了理论分析和对比,给出了异构电路评价方法和选择策略.以8线—3线编码器作为设计实例,实验结果证明了基于多目标进化设计的异构电路所组成的容错系统具有更好的容错能力.

A design method based on evolvable hardware is proposed for N-modular redundancy fault-tolerant system with different structures. Firstly, a multi-objective genetic algorithm is improved and is used to design some target digital circuits of multi-modular redundant system. Secondly, an evaluation strategy of multi-modular digital circuits with different structures is presented to optimize the design of N-modular system with different structures. Finally, the designed digital circuits with different structures are used to form the N-modular redundancy fault-tolerant system so as to enhance the reliability of the fault-tolerant system. The fault-tolerant capability of target circuits evolved by single-objective and multi- objective genetic algorithms and that of the systems composed of digital circuits with the same and different structures are analyzed theoretically and compared. An evaluation method and a selection strategy are designed for digital circuits with different sh：uctures. Experiments are made with 8-3 coder as an example, and the experimental results prove that the fault-tolerant system composed of circuits with different structures evolved by multi-objective genetic algorithm can obtain better fault-tolerant capability.