一种高档FPGA可重构配置方法

Reconfigurable Method of Advanced FPGAs

在多模式导航接收机中,FPGA可重构技术能将硬件资源进行时分复用,从而大大降低系统的复杂性和成本。在对高档FPGA可重构技术深入研究的基础上,设计了用CPLD+FLASH对FPGA进行重构配置的硬件电路,给出了对CPLD进行硬件描述的Verilog HDL程序,结果表明该方法是可行的。

In the multi-mode navigation receiver, reconfigurability technology of FPGAs can realize different function using the same hardware resource at alternative time. Based on the research of the reconfigurability technology of top grade FPGAs, the hardware has been designed using the Flash＋CPLD scheme to reconfigure the FPGA, and the Verilog HDL program of the CPLD is provided . The result indicate that the method is feasible.