基于时钟恢复系统中的锁相环电路的设计

The Design of PLL Circuits Based on Clock Recovery System

本文主要设计了基于相位控制技术的时钟恢复系统的PLL锁相环路。分别对各单元电路结构--鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、分频器进行设计。采用2.5V,0.25μm First Silicon CMOS工艺来实现,并在SPICE平台下进行仿真。仿真结果表明,该PLL环路的锁定时间仅为2.4us,并且输出的频谱呈现出较高的纯度,具有高速、低噪声的特点。

In this paper, a PLL circuits based on clock recovery system which based on phase controlled technology is studied. All units were designed by the following orders PFD,charge pump,LPF,VCO and frequency？divider. All the design is fabricated in a 2.5V, 0.25μm first silicon CMOS process. The simulation results show that the acquisition time is only 2.4us, and the outputs frequency spectrum presents a higher purity. So the PLL circuits have the characteristic of high-speed and low-noise.