MPCore Cache带宽测试及其对并行编程的影响

Test of the MPCore cache bandwidthand considerations for efficient software execution

片上多处理器(CMP)在不提高处理器频率的情况下能提高CPU的性能,但多核处理器在对共享数据进行并行运算时存在cache一致性问题,导致每个CPU的数据传输带宽和程序运行效率降低。针对这个问题,在Linux操作系统环境下对MPCore各级cache性能及cache-to-cache传输性能进行了测试,结果表明采用cache-to-cache的数据传输方式能有效降低主存的负载。根据测试结果,提出在MPCore处理器上采用SPPM(synchronized pipelined parallelism model)模型进行并行编程的方法,通过实验证明在进行并行运算时,SPPM模型的运行效率高于SDM (the spatial decomposition model)模型。

Chip multiprocessors （CMPs） provide high CPU performance without improving the frequency of processor, but when the CMP deals with share data, the cache coherency is problem that tends to put more pressure on the memory interface than their single-thread counterparts and decrease the efficiency of the parallel program. Aiming at this problem, the bandwidths of different level caches and cache-to-cache transfer are tested in Linux environment. The test result shows that the cache-to-cache transfer can decrease the load of main memory. According to the test result, the SPPM （synchronized pipelined parallelism model） that used to design the parallel program on MPCore is presented. The experiment results show the parallel program that adopting SPPM has more efficient than SDM.