基于Wishbone SoC总线接口的高性能SDRAM控制器

High Performance SDRAM Controller with Wishbone SoC Bus Interface

介绍了一种基于Wishbone SoC总线接口的SDR SDRAM控制器的设计及在FPGA上的实现,对影响其性能的关键因素做了分析。与同类的设计相比,该控制器使用高性能、简单灵活、可复用性高的片上总线接口对SDRAM的控制命令进行了完全的封装,可以进行无限长的Wishbone总线猝发传输,并自动插入刷新操作,当一次传输跨越不同的Bank和Row时,自动插入等待周期并进行切换,可达到很高的存取效率。

An SDR SDRAM controller based on Wishbone SoC bus interface and its implementation method in FPGA are proposed. And the main factor associated with its performance is discussed. Compared with other SDRAM controller design, it has a high performance and user-friendly SoC bus interface, which completely encap- sulates the SDRAM control protocol. It implements the unlimited burst transmission, automatically insertion of Refresh cycle, and automatically switching when one transmission cycle crosses over banks and rows. The controller can achieve 90% SDRAM access efficiency.